New techniques for low power caches

Power consumption is one of the major concerns in modern embedded computing systems. On-chip caches represent a sizeable fractions of the total power consumption of microprocessors. Its reduction is becoming fundamental to develop both low-power and high-performance systems. Although large caches can improve performance, they equally increase the power consumption. The operation frequency and the transistor size are other important factors of the power consumption. Basically, cache power consumption is mainly due to two factors: dynamic switching power (charging and discharging capacitors) and static power (short-circuit currents). Static power is increasing in importance in newer CMOS technologies (like e.g. 0.65 μm technology) and it is surpassing dynamic power. Recently, many studies describe new techniques for the reduction of both static and dynamic power consumption. A new proposal for the reuse of the charge potentially lost during the discharging of unused cells is presented. Two ideas are illustrated. The first uses the residual charge from cell put into drowsy-mode to charge the neighbors cell. The second and less complex idea is based on the use of the residual charge to drive the nearest cell drowsy bit, through a adequate network and circuitry.